During manufacture, circuit assemblies (e.g., printed circuit boards and Multi-Chip Modules) need to be tested for interconnect defects such as open solder joints, broken connectors, and bent or misaligned leads (e.g., pins, balls, or spring contacts). One way to test for such defects is via capacitive lead-frame testing. FIGS. 1 & 2 illustrate an exemplary setup for capacitive lead-frame testing. FIG. 1 illustrates a circuit assembly 100 comprising an integrated circuit (IC) package 102 and a printed circuit board 104. Enclosed within the IC package is an IC 106. The IC is bonded to the leads 108, 110 of a lead-frame via a plurality of bond wires 112, 114. The leads, in tum, are meant to be soldered to conductive traces on the printed circuit board. Note, however, that one of the leads 108 is not soldered to the printed circuit board, thereby resulting in an “open” defect.
Positioned above the IC package 102 is a capacitive lead-frame test assembly 116. The exemplary test assembly 116 shown comprises a sense plate 118, a ground plane 120, and a buffer 122. The test assembly is coupled to an alternating current (AC) detector 124. A first, grounded test probe, TP_1, is coupled to lead 110 of the IC package. A second test probe, TP_2, is coupled to lead 108 of the IC package. The second test probe is also coupled to an AC source 126.
FIG. 2 shows an equivalent circuit for the apparatus shown in FIG. 1. In the equivalent circuit, CSense is the capacitance seen between the sense plate 118 and the lead 108 being sensed, and CJoint is the capacitance seen between the lead 108 and the conductive trace (on the printed circuit board) to which the lead is supposed to be soldered. The switch, S, represents the quality of the lead being tested. If the lead being tested is good, switch S is closed, and the capacitance seen by the AC detector is CSense. If the lead being tested is bad, switch S is open, and the capacitance seen by the AC detector is CSense*CJoint/(CSense+CJoint). If CSense is significantly larger than any possible CJoint, a bad lead will result in the AC detector seeing a capacitance near CJoint. As a result, the AC detector must have sufficient resolution to distinguish CSense from CJoint.
Additional and more detailed explanations of capacitive lead-frame testing are found in U.S. Pat. No. 5,557,209 of Crook et al. entitled “Identification of Pin-Open Faults by Capacitive Coupling Through the Integrated Circuit Package”, and in U.S. Pat. No. 5,498,964 of Kerschner entitled “Capacitive Electrode System for Detecting Open Solder Joints in Printed Circuit Assemblies”.
Over the years, various factors have interfered with the success of capacitive lead-frame testing. One factor is a lack of capacitive coupling between an IC lead-frame and a tester's sense plate. This problem is largely traced to the on-going miniaturization of IC packages and their lead-frames, as well as the imposition of ground shield and heat sinks between lead-frames and the sensor plate (some of which are internal to an IC's package). The miniaturization of lead-frames is also exacerbated by “area connection” packages. In an area connection package, the package's lead-frame is laid out as an array on a surface of the package, rather than in rows along the edges of the package. Examples of package area connections include ball grid arrays (BGAs; a lead-frame comprising a plurality of solder balls on a surface of a package) and land grid arrays (LGAs; a lead-frame comprising a plurality of stenciled or screened contact pads on a surface of a package). Area connection packages can be advantageous in that they often minimize the lengths of signal traces coupling a package's IC to its lead-frame. They can also interfere with capacitive lead-frame testing in that they sometimes make it difficult to position the sense plate of a capacitive lead-frame tester in close enough proximity to their lead-frames. They can also present a problem as they have a limited area for sensing purposes.
One way to address some of the problems of IC miniaturization is disclosed in U.S. Pat. No. 6,087,842 of Parker et al. entitled “Integrated or Intrapackage Capability for Testing Electrical Continuity Between an Integrated Circuit and Other Circuitry”. This patent teaches the placement of a capacitive sensor interior to an IC package. If the placement of such sensor is carefully chosen, the capacitive coupling between the sensor and a package's lead-frame can be increased-in part because the interior placement of the capacitive sensor can circumvent shielding and heat dissipation structures of the IC package.
Another factor that has interfered with the success of capacitive lead-frame testing is the ratio of non-signal leads to total leads on an IC package. As ICs have become more complex and operate at higher frequencies, the ratio of non-signal leads as a fraction of total leads has increased. Typically, the non-signal leads supply power and ground connections, and are redundantly connected in parallel (either on a printed circuit board, within an IC package, or within an IC itself). Capacitive lead-frame testing is not designed to detect opens on such leads. Thus, a significant fraction of IC leads could suffer from opens that cannot be tested.
Another factor that has interfered with the success of capacitive lead-frame testing is socket-mounted IC packages. These packages do not mount directly to a board, but are mounted in sockets that allow them to be added or replaced after a board is manufactured. This adds a layer of complexity to testing in that proper connection between the board and package requires proper connection between the board and socket. If the package is placed in the socket, both sets of connections (i.e., between board and package, and between board and socket) can be tested at once via In-Circuit test, Boundary-Scan test, capacitive lead-frame test, and so on. However, all of these techniques depend on the inserted device's inherent testability for opens coverage; and even if the inserted device is suited to application of these techniques, only signal leads will be adequately tested, and redundant power and ground connections will only be “grossly” tested. If the inserted device has poor testability, neither the inserted device nor the socket will be adequately tested. Also, sockets are easily damaged, so there are opportunities to damage a socket that must be minimized during manufacture, shipping, handling, attachment to the printed circuit board, testing or during insertion of the IC into the socket.
Yet another factor that has frustrated the success of capacitive lead frame testing is the addition of more and more connectors to printed circuit assemblies, such as edge connectors, motherboard connectors, daughter board connectors, etc. These connectors have delicate connector pins that are easily bent or damaged during mating and when left open and unprotected. Connectors must be functional and free of defects, such as open, shorted or misdirected electrical paths. Connectors are becoming denser and more complex., adding to the causes of printed circuit assembly failures during manufacturing, handling and test. The amount of force required to mate these denser connectors is significant and can easily damage or destroy misaligned connector pins, the attachment point between the connector and the circuit assembly or the circuit assembly. Today, automated machines generally handle most aspects of manufacturing, handling and testing of circuit assemblies. However, mating and de-mating of circuit assembly connectors is generally done manually, due to the forces involved and the potential for damage. Thus, it is desirable to limit mating and de-mating circuit assembly connectors during manufacturing, handling and test, in order to avoid damaging the connector and the circuit assembly and to limit manual handling of circuit assemblies to save time and cost.
Accordingly, there is a need for a method and apparatus to test the electrical paths through connectors on printed circuit assemblies that can be automated, while minimizing the risk of damaging the connector or the circuit assembly, reducing testing and handling costs, and increasing testing and handling throughput.